Summary: This contribution defines systolic digit-serial architectures for fields \(\text{GF}(p^m)\). These architectures are scalable in the sense that their instantiations support multiplication in different fields \(\text{GF}(p^m)\) for which \(p\) is fixed and \(m\) is variable. These features make the multiplier architectures suitable for ASIC as well as FPGA implementations. In addition, the same architectures are easily applicable to tower fields \(\text{GF}(p^m)\) for a given ground field \(\text{GF}(p)\), where \(q\) itself is a prime power. We simulated the basic cell of a systolic LSDE multiplier on \(0.18 \mu \)m CMOS technology to verify the functionality of the architectures. Finally, we provide specific values for \(\text{GF}(2^m)\)) and \(\text{GF}(3^m)\)) fields which are of particular interest in recent cryptographic applications, for example, the implementation of short signature schemes based on the Tate pairing.
For the entire collection see [Zbl 1029.00080].